1. Field of the Invention
The present invention relates to a printed circuit board having an embedded electronic component with a via hole.
2. Description of the Related Art
It is known technology to embed passive electronic components such as resistors and capacitors and active electronic components such as integrated circuit chips in a printed circuit board, to increase the mounting density of the board. Embedded integrated circuit chips must have small packages, so it is advantageous to use chip scale packages, which are barely larger than the integrated circuit chip itself, or chip size packages, which in plan view are the same size as the chip itself. Recently, wafer level chip size packages have become prevalent. A wafer level chip size package (WCSP) is simply a dielectric layer covering the chip surface on which the integrated circuit is created, with conductive terminals such as solder bumps providing electrical access to the integrated circuitry. This type of package is formed on the semiconductor wafer from which the chip is fabricated, before the wafer is diced into individual chips.
A conventional process for forming a circuit board with embedded WCSP components is illustrated in FIGS. 1 to 3.
In FIG. 1, WCSP components 1 that have been tested after package formation and are known to be non-defective are attached to a substrate 2 by means of a die bonding adhesive 3. Next, the surface of the substrate 2 on which the WCSP components 1 are mounted is sealed with a dielectric layer 4 that surrounds and protects the WCSP components 1 as shown in FIG. 2. A second dielectric layer 5 is formed on the first dielectric layer 4; then a conductive wiring pattern 7 is formed on the second dielectric layer 5, making electrical contact with the WCSP components 1 through openings in the second dielectric layer 5. Next, a further dielectric layer 6 is formed, covering the conductive wiring pattern 7, and solder balls 8 are formed as external terminals to complete the circuit board, as shown in FIG. 3.
In a variant of this process, the first two dielectric layers 4, 5 are formed simultaneously.
FIG. 4 shows a conventional circuit board 20 having components 10, 11, 12 mounted on its surfaces as well as having an embedded WCSP component 21. The WCSP component 21 is attached to a substrate 13 by a die bonding adhesive 14 and is sealed in a first dielectric layer 15, which is covered by a second dielectric layer 16. (The two dielectric layers 15, 16 may be formed as a single combined layer.) A conductive wiring pattern 17 is formed on dielectric layer 16, and the first semiconductor device 10 and the chip component 12 are mounted in electrical contact with the wiring pattern 17. Another wiring pattern 19 formed on the opposite side of the circuit board 20, on the undersurface of the substrate 13, and the second semiconductor device 11 is mounted on this surface, making electrical contact with the wiring pattern 19. The semiconductor devices 10, 11 are, for example, integrated circuit devices. The chip component 12 may be either an active component or a passive component.
The first semiconductor device 10 is electrically coupled to the second semiconductor device 11 through the wiring patterns 17, 19 and a conductive member or conductor 18 formed in a via hole extending from one surface to the other surface of the circuit board 20. The WCSP component 21 is electrically coupled to the first semiconductor device 10 through wiring pattern 17, and to the second semiconductor device 11 through the wiring patterns 17, 19 and a conductor 22 formed in another via hole. Further information can be found in Japanese Patent Application Publication No. 2003-347502.
One problem with the conventional circuit board 20 in FIG. 4 is that the long length of the electrical connection indicated by the arrow 23 from the WCSP component 21 through wiring pattern 17, conductor 22, and wiring pattern 19 to the second semiconductor device 11 impedes the high-speed transmission of electrical signals from the WCSP component 21 to this semiconductor device 11.
As the complexity of the semiconductor devices mounted on circuit boards increases year by year, the complexity of the wiring patterns on their surfaces and the number of electrical connections necessary between the surfaces also increases, requiring a large number of via holes to be formed. The embedding of WCSP components in such a circuit board is subject to layout constraints, not only because the embedded WCSP components must avoid the numerous via holes, but also because the embedded WCSP components require the formation of additional via holes for electrical connections that pass between the two surfaces of the circuit board as illustrated in FIG. 4. These constraints pose another problem; if they could be partially removed, additional layout space could be obtained and the component mounting density could be increased.